1. Field of the Invention
The present invention relates to the field of digital electronic systems. More particularly, the present invention relates to the field of interface circuits used for the communication of information between an external memory module and an integrated circuit (IC) chip.
2. Related Art
Digital computer systems, and many electronic devices, typically contain one or more integrated circuit (IC) chips that are coupled to an external memory module using a memory interface. The memory interface provides communication between the IC chip and the memory module and contains address bus lines, data bus lines and control signal lines. Recent developments in the computer industry have placed large demands on the amount of memory and signal processing capabilities required of digital computer systems. These demands have lead to larger and larger data bus sizes to improve data storage, data throughput and data communication bandwidths. Generally, the larger the bus size, the greater its bandwidth. For instance, it is not uncommon for a memory interface to contain a 16-bit, a 32-bit or a 64-bit data bus. A typical 32-bit data bus can move four 8-bit bytes worth of data in a single clock cycle.
Memory modules often contain a collection of separate memory units ("chips") that are addressed by the memory interface and are used collectively to provide the memory requirements for the IC chip. For instance, to provide a memory module having a 32-bit word length and having a storage capacity of 32K words, four 8-bit memory chips can be used in parallel within the memory module. FIG. 1 illustrates a memory module 10 having four 8-bit memory IC chips 20-23, each memory IC chip having a 32K byte capacity. An IC chip 35 is also shown. Each of the four memory IC chips 20-23 of module 10 receives an entire address bus (not shown) in parallel from the memory interface and also each memory IC chip receives a respective 8-bit portion of a 32-bit data bus (not shown) of the memory interface.
Importantly, in order to allow the words of the memory module 10 to be individually byte accessible to the IC chip 35, each of the memory IC chips 20-23 of memory module 10 requires a separate set of control signals which are shown in FIG. 1. The IC chip 35 generates these separate control signals for memory module 10. For example, there are four separate sets of control signals 30-33 shown in FIG. 1. Each set of control signals is used for a respective memory IC chip and each set of control signals includes a chip enable (CE), a write enable (WEN) and an output enable (OE) signal. The syntax "N" merely indicates an active low condition. By requiring a separate set of control signals for each memory IC chip, the pin count for the IC chip 35 is increased to accommodate the total number of control signals. For instance, at least 12 pins are required to provide the control signal interface of FIG. 1 to provide byte accessibility.
There are many advantages of reducing the pin count for an IC chip. For instance, by making the pin count smaller, the size of the IC chip can be reduced. Often, it is the number of pins, not necessarily the size of the integrated circuit die, that has the largest impact on the size of a chip device. The term "pad limited" refers to IC designs whose chip size is limited by the number of pads associated with the chip device, not its integrated circuit die size. There are many advantages in reducing the size of the chip device. By reducing the size of the IC chip, it can be manufactured more economically and, further, it can advantageously be used in more designs where size is a critical factor (e.g., in portable devices, in cell phones, etc.). Also, smaller sized IC chips generally dissipate less power. Therefore, by reducing the size of the IC chip, it can be made available for more designs where reduced power dissipation is an important consideration (e.g., in battery operated devices, in portable devices, etc.). Lastly, by reducing the pin count on the IC chip, its manufacturing and operational quality improves by reducing the error-prone tasks pad bonding. Therefore, an IC chip having reduced pin count can be made in greater yields thereby again reducing its manufacturing costs.
Heretofore, byte accessibility within for a memory module in combination with an IC chip has required increased pin count for the IC chip due to the requirement that each memory IC chip receive separate control signals. Therefore, heretofore, integrated circuit devices offering byte accessibility of a memory module, as described above, have not enjoyed the size, reliability and economical benefits of a reduced pin count IC chip.
Accordingly, what is needed is an efficient memory interface between an integrated circuit and an external memory module that allows byte accessibility of the memory module. What is needed further is a memory interface design having a large data bus but avoiding the problems associated with the high pin count required of the separate control signals of the prior art. The present invention provides these advantageous capabilities. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.